US 2010/0165769 A1 · SEMICONDUCTOR MEMORY DEVICE HAVING AUTO-PRECHARGE FUNCTION

Abstract

To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write recovery period synchronously with the second internal clock. The second clock generation circuit activates the second internal clock when auto-precharge is designated, and deactivates the second internal clock when the auto-precharge is not designated. With this configuration, the recovery counter does not perform any counting operation when an auto-precharge function is not operated, and thus unnecessary power consumption can be prevented.

Claims16

Dependent claims

A semiconductor memory device having an auto-precharge function of automatically resetting a word line and of precharging a bit line after ending a read operation or a write operation, the semiconductor memory device comprising:

first and second clock generation circuits that generate first and second internal clocks, respectively;
a first counter circuit that counts at least latency indicating number of clocks since issuance of a read command until an output of read data or number of clocks since issuance of a write command until an input of write data, synchronously with the first internal clock;
and
a second counter circuit that counts at least a write recovery period since completion of an output of the read data or completion of an input of the write data until start of auto-precharge, synchronously with the second internal clock, wherein
the second clock generation circuit activates the second internal clock when the auto-precharge is designated at time of issuance of the read command or the write command, and deactivates the second internal clock when the auto-precharge is not designated at the time of issuance of the read command or the write command.

2 more elements

A semiconductor memory device comprising:

a plurality of command pins that supplied with an external command including first and second commands that are issued in this order;
a plurality of address pins that supplied with an external address signal including first and second address signals that are supplied in this order, the first address signal being supplied to a first set of address pins including a predetermined address pin, the second address being supplied to a second set of address pins excluding the predetermined address pin;
a memory cell array having a plurality of word lines and a plurality of bit lines;
a row decoder that selects any of the word lines based on the first address signal that is supplied synchronously with the first command;
a column decoder that selects any of the bit lines based on the second address signal that is supplied synchronously with the second command;
a clock generation circuit that activates an internal clock when the predetermined address pin is supplied with a first logic level synchronously with the second command and deactivates the internal clock when the predetermined address pin is supplied with a second logic level synchronously with the second command;
and
a recovery counter circuit that resets the word lines and starts a precharge of the bit lines by counting an internal clock signal.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having auto-precharge function

Life of this patent

Semiconductor memory device having auto-precharge function

Life of this patent

Abstract

Claims16