Bit line precharge circuit and a semiconductor memory apparatus using the same
AssigneeHynix Semiconductor Inc.
InventorHyung Sik Won
Life of this patent
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Abstract
A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal.
Claims30
A bit line precharge circuit, comprising:
- a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal;
- a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines;
- and
- a second precharge unit configured to apply the bit line precharge voltage to the bit line in response to the second precharge signal.
A semiconductor memory apparatus that performs different bit line precharge operations depending on whether or not a short fail occurs between a bit line and a word line, wherein the bit line precharge operation is performed by generating first and second precharge signals in response to receiving a bit line equalizing signal when the short fail occurs and the bit line precharge operation is performed by receiving the bit line equalizing signal when the short fail does not occur.
A semiconductor memory apparatus that includes a first precharge unit and a second precharge unit and performs different bit line precharge operations depending on whether or not a short fail occurs between a bit line and a word line, wherein the bit line precharge operation is performed through the first and second precharge units when the short fail occurs and the bit line precharge operation is performed through the first precharge unit when the short fail does not occur.
Dependencies are inferred from the claim text.