Asymmetric Sense Amplifier

An asymmetric sense amplifier comprising:

• a first pull up field effect transistor (FET) with its channel coupled between a supply voltage and a first output node;
• a first pull down FET with its channel coupled between the first output node and electrical ground by way of a channel of an enable FET;
• a second pull up FET with its channel coupled between the supply voltage and a second output node;
• a second pull down FET with its channel coupled between the second output node and electrical ground by way of the channel of the enable FET;
• a first gate FET with its channel coupled between a data input and the first output node;
• a second gate FET with its channel coupled between the supply voltage and the second output node;
• a first precharge FET with its channel coupled between gate terminals of the first pull up FET and the second pull up FET;
• wherein gate terminals of the first pull up FET and the first pull down FET are coupled to the second output terminal;
• wherein gate terminals of the second pull up FET and the second pull down FET are coupled to the first output terminal;
• wherein gate terminals of the first gate FET and the second gate FET are coupled to a gate control signal;
• wherein a gate terminal of the precharge FET is coupled to a precharge control signal;
• wherein a width of the channel of the second pull down FET is wider than a width of the channel of the first pull down FET;
• and
• wherein a width of the channel of the second gate FET is wider than a width of the channel of the first gate FET.

A memory device comprising:

• an array of memory cells coupled to a plurality of row lines and column lines;
• a row decode coupled to the plurality of row lines, and to an address decode, the row decode configured to activate a selected row line decoded from a row address provided by the address decode;
• a column decode coupled to the plurality of column lines, and to the address decode, the column decode configured to activate a selected column line decoded from a column address provided by the address decode;
• a sense amplifier coupled to the column decode, the sense amplifier configured to detect a value stored in a memory cell activated by the selected row line and the selected column line, to enhance the detection of a one (1) stored in the memory cell by having a first pull down transistor with a channel width that is larger than a second pull down transistor, wherein the first pull down transistor is coupled to a first data input and the second pull down transistor is coupled to a second data input and the first data input is coupled to a supply voltage and the second data input is coupled to the selected column line, and to enhance the detection of a zero (0) stored in the memory cell by having a first gate transistor with a channel width that is larger than a second gate transistor, wherein the first gate transistor is coupled to the first data input and the second gate transistor is coupled to the second data input.