Semiconductor Memory Device
AssigneeHynix Semiconductor Inc.
InventorYoung-Han Jeong
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells, and at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.
Claims19
A semiconductor memory device, comprising:
- a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells;
- and
- at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.
A semiconductor memory device, comprising:
- a plurality of fuse sets configured to output a plurality of redundancy addresses according to a programming state of a plurality of fuses in response to address information corresponding to a plurality of memory cells in each memory bank and corresponding to a plurality of memory banks where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells;
- and
- at least one activation controlling unit configured to control activation of the plurality of fuse sets in response to a selection signal corresponding to the memory bank.
A method comprising:
- forming a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells;
- outputting a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells;
- and
- selectively turning on a plurality of transistors connected to the current path to drain current through the current path, wherein a number of the transistors that are turned on changes based on at least one detection signal.
19 The method of claim 17, wherein the drain current changes a logic state of a latch circuit.
Dependencies are inferred from the claim text.