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AssigneeSTMicroelectronics S.r.l.
InventorsLuca PETRALIA, Danilo LAMEDICA, Carmela CALAFATO, Salvatore CAPICI
Estimating the term…
The memory device (for example, a DRAM) includes a matrix of memory cells arranged in a plurality of rows and columns (for example, organized in pairs), which include redundancy rows and columns for replacing defective rows and columns. Each one of a plurality of bit lines is connected to the cells of a corresponding column, and each one of a plurality of word lines is connected to the cells of a corresponding row. A bit line driver is used for biasing the bit lines and a word line driver is used for biasing the word lines. Each one of a plurality of selectors is arranged along a potential conduction path between the bit line driver and the word line driver through a set of corresponding word lines and bit lines. A selection driver is used for setting each selector to a first resistance (for example, closed) if the corresponding rows and columns are non-defective or to a second resistance higher than the first resistance (for example, open) if at least one of the corresponding rows and columns is defective.
A memory device comprising:
An electronic system comprising:
A method for operating a memory device including a matrix of memory cells arranged in a plurality of rows and columns, a plurality of bit lines each being connected to the memory cells of a corresponding column, a plurality of word lines each being connected to the memory cells of a corresponding row, a bit line driver for biasing the bit lines, a word line driver for biasing the word lines, a plurality of selectors each being arranged along a potential conduction path between the bit line driver and the word line driver through a set of corresponding word lines and bit lines, the method comprising:
Dependencies are inferred from the claim text.