Semiconductor memory device and method for operating the same

A semiconductor memory device, comprising:

• a data input/output unit configured to receive and store data in response to an input strobe signal and to output the stored data to a memory cell in response to an output strobe signal;
• a clock dividing unit configured to output multi-phase clocks by dividing a data clock;
• a data input control unit configured to output the input strobe signal, wherein the input strobe signal is synchronized with the multi-phase clocks, in response to a write enable signal;
• and
• an output strobe signal generation unit configured to output the output strobe signal, wherein the input strobe signal is synchronized with a system clock, in response to the write enable signal.

A method for operating a semiconductor memory device, comprising:

• generating a write enable signal and a write training signal enabled in a write training mode in response to a write command;
• generating a core enable signal, wherein the core enable signal is synchronized with a system clock in response to the write enable signal;
• generating an output strobe signal by delaying the core enable signal by a predetermined time;
• disabling the core enable signal based on the write training mode in order to transmit the disabled core enable signal to a memory cell, wherein the memory cell is enabled by the enabled core enable signal;
• generating multi-phase clocks by dividing a data clock;
• generating an input strobe signal synchronized with the multi-phase clocks in response to the write enable signal;
• and
• receiving and storing data in response to the input strobe signal and outputting the stored data to the memory cell in response to the output strobe signal.