Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHironobu FURUHASHI
Life of this patent
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Abstract
A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region.
Claims20
A semiconductor memory device comprising:
- a semiconductor layer;
- a source layer and a drain layer in the semiconductor layer;
- an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data;
- a gate dielectric film on the body region;
- and
- a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region.
A method of driving a semiconductor memory device comprising a source layer, a drain layer, an electrically floating body region accumulating or discharging charges to store logical data, and a first gate electrode and a second gate electrode above one body region separated on the drain layer side and the source layer side, respectively,
- the method comprising:
- making a voltage applied to the first gate electrode be lower than a voltage applied to the second gate electrode when data is written in the memory cell.
A manufacturing method of a semiconductor memory device comprising a memory cell comprising a gate electrode, a source layer, a drain layer, and an electrically floating body region accumulating or discharging charges to store logical data, the manufacturing method comprising:
- forming a gate dielectric film on a semiconductor layer provided on a buried insulation film;
- forming a mask material on the gate dielectric film;
- removing the mask material corresponding to a part where the gate electrode is to be formed in order to form a trench in the mask material;
- forming a material for the gate electrode on side surfaces of the trench so that a first gate electrode is formed on one side surface of the trench and a second gate electrode is formed on the other side surface thereof;
- forming an intergate dielectric film between the first gate electrode and the second gate electrode;
- removing the mask material;
- forming a side wall film on the respective side surfaces of the first gate electrode and the second gate electrode;
- and
- introducing an impurity using the first gate electrode, the second gate electrode, the intergate dielectric film, and the side wall film as a mask to form the source layer and the drain layer.
Dependencies are inferred from the claim text.