US 2010/0165753 A1 · METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY DEVICE

Abstract

A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines.

Claims21

Dependent claims

A memory device comprising:

a plurality of bit lines;
a plurality of nodes, wherein each node is to facilitate access of a respective one of the bit lines;
and
a logic circuit comprising a plurality of transistors, each transistor coupled with the respective one of the bit lines and with a respective one of the nodes, wherein the transistors are to reduce leakage of the bit lines when deactivated.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

12/345,442Filed 29 Dec 2008

Published

1 Jul 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C
Static stores

Method and apparatus for reducing leakage in bit lines of a memory device

Life of this patent

Method and apparatus for reducing leakage in bit lines of a memory device

Life of this patent

Abstract

Claims21