Verification circuits and methods for phase change memory array

A verification method for a phase change memory array, comprising:

• reading a memory cell of the phase change memory array to obtain a sensing voltage;
• comparing the sensing voltage and a reference voltage;
• and
• when the sensing voltage is smaller than the reference voltage, providing a writing current to the memory cell and gradually increasing the writing current until the sensing voltage corresponding to the writing current is larger than or equal to the reference voltage.

A verification method for a phase change memory array, comprising:

• providing a writing current to a first memory cell of the phase change memory array and gradually increasing the writing current until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage;
• recording the current magnitude of the writing current as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage;
• reading a second memory cell of the phase change memory array to obtain a second sensing voltage;
• determining whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage;
• and
• providing the writing current with the reference current magnitude to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state.