Phase change memory device
AssigneeMicron Technology, Inc.
InventorFabio PELLIZZER
Life of this patent
Estimating the term…
Abstract
A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
Claims23
A phase change memory device, comprising a memory array (1) formed by a plurality of groups (7) of memory cells (2), the memory cells being arranged in rows and columns and connected at cross-points of word lines (6) and data bitlines (5), each memory cell (2) comprising a phase change memory element (3) and a selection switch (4), characterized by a plurality of reference cells (2a-2c), each reference cell (2a-2c) comprising an own phase change memory element (3a-3c) and an own selection switch (4a-4c) and being associated to at least one group (7) of memory cells.
The phase change memory device according to claim I, wherein each group (7) of memory cells (2) and the associated reference cell (2a-2c) extend along a same word line (6) and the reference cells (2a) are connected to reference bitlines (5a-5c).
A system comprising:
- a processor (510);
- an input/output device (520) coupled to said processor;
- and
- a memory (530) coupled to said processor, said memory including phase change memory device comprising:
- a memory array (1) formed by a plurality of groups (7) of memory cells (2), the memory cells being arranged in rows and columns and connected at cross-points of word lines (6) and data bitlines (5), each memory cell (2) comprising a phase change memory element (3) and a selection switch (4), characterized by a plurality of reference cells (2a-2c), each reference cell (2a-2c) comprising an own phase change memory element (3a-3c) and an own selection switch (4a-4c) and being associated to at least one group (7) of memory cells.
A method of reading a phase change memory device comprising a memory array (1) formed by a plurality of groups (7) of memory cells (2), the memory cells being arranged in rows and columns and connected at cross-points of wordlines (6) and data bitlines (5), each memory cell (2) comprising a phase change memory element (3) and a selection switch (4), the memory device further including a plurality of reference cells (5a), each reference cell (5a) comprising phase change memory element (3) and an selection switch (4). being associated to at least one group (7) of memory cells and being connected to a reference bitline, characterized by:
- comparing an electrical behavior of said memory and of said reference cells (2a-2c).
A method of programming a phase change memory device comprising a memory array (10) formed by a plurality of groups (7) of memory cells (2), the memory cells being arranged in rows and columns and connected at cross-points between word lines (6) and data bitlines (5), each memory cell (2) comprising a phase change memory element (3) and an ovonic threshold switch (4), the memory device further including a plurality of threshold reference cells (Sa), each threshold reference cell (5a) comprising an own phase change memory element (3) and an own ovonic threshold switch (4), being associated to a group (7) of memory cells and being connected to a reference bitline, comprising programming a group of memory cells (2) in at least a set state and a reset state, characterized by:
- programming a threshold reference cell (2a) associated to the group of memory cells (2) being programmed into the set state;
- and
- programming the memory cells (2).
Dependencies are inferred from the claim text.