US 2010/0165716 A1Published application

Nonvolatile memory with ovonic threshold switches

AssigneeSTMicroelectronics S.r.l.

InventorsDerchang Kau, Greg Atwood, Gianpaolo Spadini

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Abstract

A memory device including a plurality of memory cells being arranged in a matrix having a plurality of rows and a plurality of columns. Each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The memory device further including a plurality of row lines each one for selecting the memory cells of a corresponding row and a plurality of column lines each one for selecting the memory cells of a corresponding column. The memory device further includes for each line among the row lines and/or the column lines a respective set of local lines each one for selecting a group of memory cells of the corresponding line, and a respective set of selection elements each one for selecting a corresponding local line of the set in response to the selection of the respective line.

Claims28

Dependent claims

A memory device, comprising:

a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation;
a plurality of array lines including a plurality of row lines configured to select the memory cells of the rows, respectively, and a plurality of column lines configured to select the memory cells of the columns, respectively;
a plurality of sets of local lines associated with a plurality of the array lines, respectively, wherein for each set, the local lines of the set are coupled to groups of memory cells of the corresponding array line, respectively;
and
a plurality of sets of selection elements associated with the sets of local lines, respectively, wherein for each set of selection elements, each selection element is configured to select, in response to a selection of the corresponding array line, a corresponding local line of the set of local lines associated with the set of selection elements.

2 more elements

An electronic system, comprising:

a processor;
input/output units for receiving and providing data;
and
a memory coupled to the processor, wherein said memory includes:
a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation;
a plurality of array lines including a plurality of row lines configured to select the memory cells of the rows, respectively, and a plurality of column lines configured to select the memory cells of the columns, respectively;
a plurality of sets of local lines associated with a plurality of the array lines, respectively, wherein for each set, the local lines of the set are coupled to groups of memory cells of the corresponding array line, respectively;
and
a plurality of sets of selection elements associated with the sets of local lines, respectively, wherein for each set of selection elements, each selection element is configured to select, in response to a selection of the corresponding array line, a corresponding local line of the set of local lines associated with the set of selection elements.

6 more elements

Dependencies are inferred from the claim text.