Random access memory architecture including midpoint reference

A random access memory architecture comprising:

• a plurality of non-symmetric memory elements, each capable of having a first state of resistance and a second state of resistance, wherein the resistance when the current is flowing therethrough in a first direction is not equal to the resistance when the current is flowing therethrough in a second direction;
• a first series connected pair of memory elements having a first resistance and a second resistance, respectively, and disposed wherein a current flows in the first direction through both of the first series connected pair of memory elements;
• and
• a second series connected pair of memory elements having a third and a fourth resistance, respectively, coupled in parallel with the first series connected pair of memory elements, and disposed wherein a current flows in the first direction through both of the second series connected pair of memory elements.

A random access memory architecture comprising:

• an array comprising at least one data column of memory cells coupled to have information stored within at least one memory cell, each memory cell including at least one non-volatile memory element programmable to one of the first state of resistance and the second state of resistance;
• a midpoint reference coupled between a first node and a second node and having a resistance between that of the first resistance state and the resistance of the second resistance state, comprising:
• a first memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state;
• a second memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the first memory cell wherein the first and second memory elements comprise a first series connected pair of elements:
• a third memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state;
• and
• a fourth memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the third memory element, wherein the third and fourth memory elements comprise a second series connected pair of memory elements;
• and
• circuitry selectively coupled to either the first or second memory element in order to sense whether the coupled first or second memory element is in the first or second resistance state, and to either the third or fourth memory element in order to sense whether the coupled third or fourth memory element is in the first or second resistance state;
• a sense amplifier coupled to the array of memory cells;
• and
• a voltage bias portion coupled to the sense amplifier, the voltage bias portion including the first, second, third, and fourth memory elements.