Robust sram memory cell capacitor plate voltage generator

A memory comprising:

• a plurality of SRAM memory cells, each SRAM memory cell respectively comprising:
• an inverter;
• a first capacitor;
• and
• a second capacitor in series with the first capacitor and sharing a common node with the first capacitor;
• and
• a voltage generator having a first transistor and configured to supply to the respective common nodes of the respective memory cells a capacitor supply voltage, the capacitor supply voltage being approximately midway between a high voltage supply level of the memory and a low voltage supply level of the memory, the first transistor being configured to generate the capacitor supply voltage by a leakage current of the first transistor.

An internal defibrillator comprising:

• a battery;
• a memory coupled to the battery, the memory having;
• a plurality of memory cells, each memory cell respectively including;
• a first capacitor;
• and
• a second capacitor in series with the first capacitor, the first and second capacitors being coupled together at a common node;
• a voltage generator including a transistor and configured to generate a capacitor supply voltage by a leakage current of the transistor, the voltage generator configured to supply the capacitor supply voltage to the respective common nodes of the respective memory cells;
• and
• electrodes coupled to the battery and the memory.

A device comprising:

• a memory cell having an inverter, the inverter having an input and an output;
• a first capacitor having a first node and a second node, the first node of the first capacitor being coupled to the input of the inverter;
• a second capacitor having a first node and a second node, the first node being coupled to the output of the inverter and the second node of the second capacitor being coupled to the second node of the first capacitor, the first node of the second capacitor being coupled to the output of the inverter;
• and
• a voltage generator having a first transistor with a gate held at the off voltage level and coupled to supply to the second nodes of the first and second capacitors a capacitor supply voltage generated from a leakage current of the first transistor.