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US 2010/0165707 A1Published application
Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Huei Chen, Jui-Jen Wu
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Abstract
An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.
Claims27
An integrated circuit structure comprising:
- a static random access memory (SRAM) cell comprising:
- a first pull-up transistor;
- and
- a first pull-down transistor forming a first inverter with the first pull-up transistor, wherein the first pull-down transistor comprises a front gate connected to a gate of the first pull-up transistor, and a back-gate decoupled from the front gate.
1 more element
An integrated circuit structure comprising:
- a word-line;
- a first Y-direction select line;
- a first static random access memory (SRAM) cell coupled to the word-line and comprising:
- a first inverter comprising:
- a first pull-up transistor;
- and
- a first pull-down transistor coupled to the first pull-up transistor and comprising a first front gate and a first back-gate;
- and
- a second inverter cross-coupled to the first inverter and comprising:
- a second pull-up transistor;
- and
- a second pull-down transistor coupled to the second pull-up transistor and comprising a second front gate and a second back-gate, wherein the first back-gate and the second back-gate are connected to the first Y-direction select line.
9 more elements
An integrated circuit structure comprising:
- static random access memory (SRAM) cells arranged as an array comprising rows and columns, wherein each of the SRAM cells comprises:
- a first inverter coupled to a power supply voltage node and comprising:
- a first pull-up transistor;
- and
- a first pull-down transistor coupled to the first pull-up transistor, wherein the first pull-down transistor comprises a first front gate and a first back-gate;
- and
- a second inverter cross-coupled to the first inverter, and coupled to the power supply voltage node, the second inverter comprising:
- a second pull-up transistor;
- and
- a second pull-down transistor coupled to the second pull-up transistor, wherein the second pull-down transistor comprises a second front gate and a second back-gate, and wherein the first back-gate and the second back-gate are interconnected;
- and
- Y-direction select lines extending in a column direction, wherein each of the Y-direction select lines is coupled to the first back-gate and the second back-gate of all of the SRAM cells in a same column.
9 more elements
Dependencies are inferred from the claim text.