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US 2010/0165704 A1Published application
Circuit and Method for a High Speed Memory Cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Hsu Wu, David Yen, Tsai-Hsin Lai
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Abstract
A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.
Claims20
A memory cell, comprising:
- a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line;
- a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node;
- and
- a storage capacitor coupled between the read word line and the storage node.
1 more element
A dynamic memory array, comprising:
- a plurality of dynamic memory cells arranged in rows and columns, each dynamic memory cell coupled to a respective read word line, a respective read bit line, a respective write word line, and a respective write bit line, and each dynamic memory cell further comprising:
- a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line;
- a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node;
- and
- a storage capacitor coupled between the read word line and the storage node.
2 more elements
Dependencies are inferred from the claim text.