Resistive memory

A resistive memory comprising:

• a plurality of sense amplifiers each having one input terminal and the other input terminal;
• a plurality of memory cell arrays which are provided in association with the plurality of sense amplifiers, respectively, the plurality of memory cell arrays including one array and the other array, the one array including a plurality of first memory cells and a plurality of first reference cells having mutually different resistance values, and the other array including a plurality of second memory cells and a plurality of second reference cells having mutually different resistance values;
• a plurality of latch circuits which hold offset information of the plurality of sense amplifiers;
• and
• a plurality of decoders which connect, at a time of read, one selected memory cell which is selected from the plurality of first memory cells of the one array, to the one input terminal of an associated one of the plurality of sense amplifiers, and connects, one selected reference cell which is selected from the plurality of second reference cells of the other array in accordance with the offset information, to the other input terminal of the associated one of the plurality of sense amplifiers.