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US 2010/0164972 A1Published application
System, method and apparatus for memory with embedded associative section for computations
AssigneeZikbit Ltd.
InventorsAvidan AKERIB, Eli EHRMAN, Moshe MEYASSED, Oren AGAM
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Abstract
A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.
Claims42
A method for data processing, the method comprising:
- storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns;
- and
- transposing multiple data words by performing a sequence of shift operations and associative operations;
- wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand;
- and storing transposed data words in the memory.
2 more elements
A method for data processing, comprising:
- storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns;
- re-arranging the input data words in response to parallel computational capabilities of an associative memory section;
- and
- processing re-arranged input-data words by performing at least one associative operation that comprises comparing in parallel multiple columns of associative memory cells to at least one comparand.
1 more element
A method for data processing, comprising:
- storing input data words in a memory that comprises multiple memory cells arranged in rows and columns;
- applying at least one associative operation on input data words;
- wherein the applying comprises comparing in parallel multiple columns of associative memory cells to at least one comparand;
- and
- utilizing address decoders for internal system transfers and outer system transfers;
- wherein the system comprises the address decoders, and registers rows that are coupled between the columns of the associative memory cells and the multiple memory cells;
- wherein internal system transfers involve storing data words in registers coupled to the address decoders.
4 more elements
A method for data processing, comprising:
- storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns;
- and
- processing multiple row-wise data word sets;
- wherein the processing comprises generating at least one carry prediction vector, wherein the processing comprises multiple shift operations and associative operations, wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand.
1 more element
A system having data processing capabilities, the system comprises:
- a semiconductor substrate;
- a memory that is formed on the semiconductor substrate and comprises multiple memory cells arranged in rows and columns;
- associative memory cells that are arranged in rows and columns;
- and
- a control logic that is coupled to the memory and to the associative memory cells;
- wherein the memory stores input data words in a row-wise manner;
- wherein the control logic controls a transposition of multiple data words by performing a sequence of shift operations and associative operations that provide transposed data words;
- wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand;
- and
- wherein the memory stores the transposed data words.
7 more elements
A system having data processing capabilities, the system comprises:
- a semiconductor substrate;
- a memory that is formed on the semiconductor substrate and comprises multiple memory cells arranged in rows and columns;
- associative memory cells that are arranged in rows and columns;
- and
- control logic that is coupled to the memory and to the associative memory cells;
- wherein the control logic controls a re-arrangement of the input data words in response to parallel computational capabilities of an associative memory section, and controls a process of re-arranged input-data words by instructing the associative memory cells to perform at least one associative operation that comprises comparing in parallel multiple columns of associative memory cells to at least one comparand.
3 more elements
A system having data processing capabilities, the system comprises:
- a semiconductor substrate,
- a memory that is formed on the semiconductor substrate and comprises multiple memory cells arranged in rows and columns;
- at least one address decoder;
- multiple registers coupled to an input output bus that is coupled to additional components;
- associative memory cells that are arranged in rows and columns, and
- a control logic that is coupled to the memory and to the associative memory cells;
- wherein the memory stores input data words;
- wherein the associative memory cells apply at least one associative operation on input data words;
- wherein the applying comprises comparing in parallel multiple columns of associative memory cells to at least one comparand;
- and
- wherein the system utilizes address decoders for internal system transfers and outer system transfers.
8 more elements
A system having data processing capabilities, the system comprises:
- a semiconductor substrate;
- a memory that is formed on the semiconductor substrate and comprises multiple memory cells arranged in rows and columns;
- associative memory cells that are arranged in rows and columns;
- and
- a control logic that is coupled to the memory and to the associative memory cells;
- wherein the memory stores input data words in a row-wise manner;
- wherein the associative memory cells process multiple row-wise data word sets;
- wherein a processing of the multiple row-wise data word sets comprises generating at least one carry prediction vector;
- wherein the processing comprises multiple shift operations and associative operations;
- wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand.
7 more elements
Dependencies are inferred from the claim text.