Display device and method for receiving low voltage differential signal at display device

A method comprising:

• receiving a clock at a data channel in response to a program signal for amplifying and delaying the clock, and receiving the clock at a clock channel for amplifying and delaying the clock, for forwarding the clock delayed and amplified thus as a plurality of compensating clocks having delay amounts different from one another;
• comparing the clock amplified and delayed at the data channel and the plurality of compensating clocks for forwarding a delay control signal;
• receiving a low voltage differential signal from the data channel in response to the program signal, amplifying the low voltage differential signal, and delaying the low voltage differential signal under the control of the delay control signal;
• generating a data restoring clock by using one of the compensating clocks;
• and
• restoring the low voltage differential signal amplified and delayed thus in synchronization with the data restoring clock.

A display device comprising:

• a skew compensating type data receiving unit for delaying clocks received in response to a program signal, comparing the clocks delayed thus to compensating clocks, setting an internal delay amount according to a result of the comparison, and delaying and forwarding a low voltage differential signals according to the delay amount set thus, wherein the skew compensating type data receiving unit includes:
• a first multiplexer for forwarding one of the clock received thus and the low voltage differential signal in response to the program signal,
• a first amplifier for amplifying a signal from the multiplexer,
• a first delay cell for delaying a signal amplified at the amplifier in response to a delay control signal, and
• a delay controller for comparing the signal delayed at the delay cell and the compensating clock to forward the delay control signal;
• a clock receiving unit for delaying the clock received thus by a fixed delay amount and forwarding the clock delayed thus as a compensating clock wherein the clock receiving unit includes:
• a second multiplexer for forwarding the clock received thus in response to the program signal,
• a second amplifier for amplifying a signal from the second multiplexer, and
• a second delay cell for delaying the signal amplified at the second amplifier and forwarding the signal delayed thus as the compensating clock;
• a clock generating unit for generating a data restoring clock by using the clock delayed thus;
• and
• a data restoring logic for restoring the low voltage differential signal delayed at the data receiving unit in synchronization with the data restoring clock.