Gate Drive Circuit, Display Device Having the Same and Method of Manufacturing the Gate Drive Circuit

A display device comprising:

• a display panel comprising a display area on which a plurality of pixel parts is formed and a peripheral area surrounding the display area, each of the pixel parts electrically connected to a gate line and a data line crossing the gate line;
• a data driving section outputting a data signal to the data lines;
• and
• a gate drive circuit comprising a shift register in which plural stages are connected to each other in series,
• an (m)-th stage (‘m’ is a natural number) comprising:
• an output part outputting the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharging the gate signal in response to a second input signal, the output part comprising a first transistor having a first channel length;
• a discharging part discharging a signal of the first node to the second voltage level in response to the second input signal;
• a first holding part maintaining a signal of the first node at a level of the gate signal, wherein the first holding part is discharged to the second voltage level in response to the first clock signal, the first holding part comprising a second transistor having a second channel length that is longer than the first channel length;
• and
• a second holding part maintaining a signal of the first node at a level of the second voltage level in response to a second clock signal.

A method of manufacturing a gate drive circuit comprising a shift register in which plural stages are connected to each other in series, each of the stages comprising a first transistor having a first channel length and outputting a clock signal as a gate signal, and a second transistor maintaining the gate signal at an off voltage in response to the first clock signal, the second transistor having a second channel length that is longer than the first channel length, the method comprising:

• patterning a gate metal layer on a base substrate to form a first gate electrode of the first transistor and a second gate electrode of the second transistor;
• forming a first active pattern having a first channel length on the first gate electrode and a second active pattern having a second channel length on the second gate electrode;
• and
• forming first source/drain electrodes on the first active pattern, and a second source electrode and a second drain electrode on the second active pattern, the second source electrode having a plurality of source electrode bars, and the second drain electrode having a plurality of drain electrode bars disposed between the source electrode bars.