Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps

An error amplifier comprising:

• a main amplifier that receives a differential input voltage that is a difference in voltages of a first differential input and a second differential input, the main amplifier driving an output;
• a compensating capacitor connected to the output, the compensating capacitor having a capacitance value that sets a single dominant pole in the error amplifier;
• a pull-up auxiliary amplifier that drives a pull-up slew current to the output when triggered by the main amplifier;
• a pull-down auxiliary amplifier that drives a pull-down slew current to the output when triggered by the main amplifier;
• a first intentional offset introduced into the pull-up auxiliary amplifier by changing a ratio of a p-channel transistor to an n-channel transistor in a same leg of transistors in the pull-up auxiliary amplifier so that the pull-up auxiliary amplifier drives the pull-up slew current to the output when the differential input voltage exceeds the first intentional offset;
• and
• a second intentional offset introduced into the pull-down auxiliary amplifier by changing a ratio of a p-channel transistor to an n-channel transistor in a same leg of transistors in the pull-down auxiliary amplifier so that the pull-down auxiliary amplifier drives the pull-down slew current to the output when the differential input voltage is more negative than the second intentional offset,
• whereby stability is achieved by the single dominant pole and speed is increased by the pull-up slew current from the pull-up auxiliary amplifier and the pull-down slew current from the pull-down auxiliary amplifier and whereby the pull-up auxiliary amplifier and the pull-down auxiliary amplifier turn on when intentional offsets are exceeded.

An amplifier comprising:

• a first current source driving a first current to a first source node;
• a first differential transistor having a channel between the first source node and a first minor-gate node, the channel controlled by a gate receiving a first differential input;
• a second current source driving a second current to a second source node;
• a second differential transistor having a channel between the second source node and a second minor-gate node, the channel controlled by a gate receiving a second differential input;
• a source degenerated resistor coupled between the first source node and the second source node;
• a first interior minor transistor having a gate connected to the first mirror-gate node, and a channel between a first cascode node and a first supply voltage;
• a first interior cascode transistor having a gate driven by a first cascode voltage, and a channel between the first mirror-gate node and the first cascode node;
• a second interior minor transistor having a gate connected to the second mirror-gate node, and a channel between a second cascode node and the first supply voltage;
• a second interior cascode transistor having a gate driven by the first cascode voltage, and a channel between the second minor-gate node and the second cascode node;
• a first leg transistor having a gate connected to a first leg node, and a channel between a second supply voltage and a second exterior cascode node;
• a second leg cascode transistor having a gate driven by a second cascode voltage, and a channel between the second exterior cascode node and the first leg node;
• a first leg cascode transistor having a gate driven by the first cascode voltage, and a channel between a first exterior cascode node and the first leg node;
• a first mirror transistor having a gate receiving the first mirror-gate node and a channel between the first exterior cascode node and the first supply voltage;
• a second output cascode transistor having a gate driven by the second cascode voltage, and a channel between a second output cascode node and an output;
• a first output cascode transistor having a gate driven by the first cascode voltage, and a channel between a first output cascode node and the output;
• a second leg transistor having a gate connected to the first leg node, and a channel between the second supply voltage and the second output cascode node;
• a second mirror transistor having a gate receiving the second mirror-gate node and a channel between the first output cascode node and the first supply voltage;
• and
• a pull-up auxiliary amplifier receiving the first minor-gate node and the second mirror- gate node, for driving a pull-up current to the output.

A differential amplifier comprising:

• first current source means for driving a first current to a first source node;
• first differential transistor means for conducting current between the first source node and a first mirror-gate node in response to a gate receiving a first differential input;
• second current source means for driving a second current to a second source node;
• second differential transistor means for conducting current between the second source node and a second mirror-gate node in response to a gate receiving a second differential input;
• source degenerated resistor means, coupled between the first source node and the second source node, for improving amplifier linearity;
• first interior mirror transistor means, responsive to a gate connected to the first mirror-gate node, for conducting current between a first cascode node and a first supply node;
• first interior cascode transistor means, responsive to a gate driven by a first cascode voltage, for conducting current between the first minor-gate node and the first cascode node;
• second interior mirror transistor means, responsive to a gate connected to the second minor-gate node, for conducting current between a second cascode node and the first supply node;
• second interior cascode transistor means, responsive to a gate driven by the first cascode voltage, for conducting current between the second minor-gate node and the second cascode node;
• first leg transistor means, responsive to a gate connected to a first leg node, for conducting current between a second supply node and a second exterior cascode node;
• second leg cascode transistor means, responsive to a gate driven by a second cascode voltage, for conducting current between the second exterior cascode node and the first leg node;
• first leg cascode transistor means, responsive to a gate driven by the first cascode voltage, for conducting current between a first exterior cascode node and the first leg node;
• first minor transistor means, responsive to a gate receiving the first minor-gate node and a channel between the first exterior cascode node and the first supply node;
• second output cascode transistor means, responsive to a gate driven by the second cascode voltage, for conducting current between a second output cascode node and an output;
• first output cascode transistor means, responsive to a gate driven by the first cascode voltage, for conducting current between a first output cascode node and the output;
• second leg transistor means, responsive to a gate connected to the first leg node, for conducting current between the second supply node and the second output cascode node;
• second minor transistor means, responsive to a gate receiving the second minor-gate node and a channel between the first output cascode node and the first supply node;
• and
• pull-up auxiliary amplifier means, receiving the first minor-gate node and the second minor-gate node, for driving a pull-up current to the output.