Power detection system and circuit for high voltage supply and low voltage devices

A power detect circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices, comprising:

• a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, the voltage divider including a first resistor and a second resistor;
• a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, the first inverter including a first PMOS transistor and a first NMOS transistor;
• a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, the native device including a second NMOS transistor with zero threshold value;
• and
• a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage, the switch including a third NMOS transistor.

A power detect system for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices, comprising:

• a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage;
• a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage;
• a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage;
• a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage;
• and
• a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.