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US 2010/0164587 A1Published application
Digital synchronous circuit
AssigneeDongbu HiTek Co., Ltd.
InventorJoong-Sug Gil
Life of this patent
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Abstract
A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.
Claims20
An apparatus comprising:
- a clock generator configured to generate a reference clock signal;
- a plurality of delays configured to delay the reference clock signal by a predetermined different time;
- a transition varying buffer configured to control input transitions of the clock signals received from the plurality of the delays;
- a transition controller configured to control operation of the transition varying buffer;
- and
- a plurality of registers driven by the clock signals from the plurality of delays.
3 more elements
An apparatus comprising:
- a clock generator configured to generate a reference clock signal;
- a first delay, a second delay and a third delay each configured to delay the reference clock signal by a predetermined different time;
- a transition varying buffer configured to control input transitions of the clock signals received from the first delay, the second delay and the third delay;
- a transition controller configured to control operation of the transition varying buffer;
- and
- a plurality of registers driven by the clock signals from the plurality of delays.
3 more elements
An apparatus comprising:
- a clock generator configured to generate a reference clock signal;
- a first delay, a second delay and a third delay each configured to delay the reference clock signal by a predetermined different time;
- a transition varying buffer configured to control input transitions of the clock signals received from the first delay, the second delay and the third delay;
- a transition controller configured to control operation of the transition varying buffer;
- and
- a first register connected to and driven by the clock signal from the first delay;
- a second register connected to and driven by the clock signal from the second delay;
- and
- a third register connected to and driven by the clock signal from the third delay.
6 more elements
Dependencies are inferred from the claim text.