Progamable control clock circuit for arrays
AssigneeInternational Business Machines Corporation
InventorsRolf Sautter, Michael Ju Hyeok Lee, Yuen Hung Chan, Juergen Pille
Life of this patent
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Abstract
A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
Claims18
A programmable clock control circuit, the circuit comprising:
- a base block configured to control operation of the programmable clock control circuit and coupled to a negative clock signal;
- a chop block configured to control the width of an output clock signal of the programmable clock control circuit and having a chop block output;
- a pulse width variation block coupled between the chop block and the base block, the pulse width variation block receiving the chop block output and providing a pulse width variation output to the base block, the pulse width variation being programmable to vary the chop block output to provide at least three different output pulse widths;
- a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output;
- and
- a clock driver circuit coupled to the clock delay block and configured to receive the clock signal output and to produce the output clock signal.
A programmable clock control circuit, the circuit comprising:
- a clock driver circuit configured to provide an output clock signal;
- a base block configured to control operation of the programmable clock control circuit;
- and
- a clock delay block between the base block and the clock driver circuit configured to receive a clocking signal from the base block and delay it an adjustable amount before the signal is transmitted to the clock driver circuit, the clock delay block including two delay control inputs.
Dependencies are inferred from the claim text.