Method and System for Setup/Hold Characterization in Sequential Cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKer-Min Chen, Ching-Hao Shaw
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKer-Min Chen, Ching-Hao Shaw
Estimating the term…
An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.
A method for setup and hold characterization in an integrated circuit cell, the method comprising:
A method for integrated circuit cell characterization, the method comprising:
An integrated circuit cell timing characterization circuit comprising:
Dependencies are inferred from the claim text.