Driving configuration of a switch

An integrated structure comprising:

• a first well realized in a substrate;
• a second well realized within the first well, said first and second wells having respectively first and second conductivity types, opposite to each other;
• a switch realized in the second well;
• first and second trenches surrounding the second well and defining a sensitive pocket;
• and
• a driving circuit realized in the sensitive and configured to drive said switch.

An ultrasonic transducer, comprising:

• a first switch including first and second transistors coupled to each other and including first and second intrinsic diodes, respectively;
• a driving circuit configured to drive said first switch, wherein the driving circuit comprises first and second output terminals coupled to the first switch and configured to supply the first switch with a first control signal for driving said first switch in a first working state and a second control signal for driving said switch in a second working state;
• and
• a latch circuit coupled between respective common gate and source terminals of said first and second transistors and configured to supply said common gate terminal with said first and second control signals, respectively, according to said working state for turning off, and respectively turning on, said first and second transistors, wherein said latch circuit comprises:
• a set resistance and a reset resistance;
• a flip-flop coupled to said common source terminal and having:
• a reset terminal coupled to said first output terminal of said driving device and to said common source terminal by the reset resistance;
• a set terminal coupled to said second output terminal of said driving device and to said common source terminal by the set resistance;
• and
• an output terminal coupled to said common gate terminal;
• and
• an activation circuit connected to said set and reset terminals of the flip-flop and to said common source terminal and configured to dynamically short-circuit said set and reset resistances during falling edges of at least one of the first and second control signals applied to the first switch.

A latch circuit, comprising

• a set resistance and a reset resistance;
• a first circuit node;
• a flip-flop including:
• a reset terminal coupled to the circuit node by the reset resistance;
• a set terminal coupled to said first circuit node by the set resistance, the reset and set terminals being configured to be driven by first and second control signals, respectively;
• and
• an output terminal;
• and
• an activation circuit coupled to said set and reset terminals of the flip-flop and to said first circuit node and configured to dynamically short-circuit said set and reset resistances during falling edges of at least one of the first and second control signals.