US 2010/0164580 A1 · HIGH SPEED CLOCK SIGNAL DUTY CYCLE ADJUSTMENT

Abstract

A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.

Claims21

Dependent claims

A method of adjusting the duty cycle of a signal, the method comprising:

generating, by a clock signal source circuit, a clock input signal that includes true and complement clock signals;
receiving, by a duty cycle correction circuit, the clock input signal;
deriving from the clock input signal, by the duty cycle correction circuit, first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets;
and
shifting, by the duty cycle correction circuit, the voltage offset of one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals.

2 more elements

Dependencies are inferred from the claim text.

High speed clock signal duty cycle adjustment

Life of this patent

High speed clock signal duty cycle adjustment

Life of this patent

Abstract

Claims21