Transit state element

A method comprising:

• receiving a clock signal, wherein the clock signal alternates between a first logic level and a second logic level;
• detecting a logical transition of an input signal on an input node;
• activating an output stage responsive to the clock signal transitioning to the second logic level and said detecting the logical transition;
• driving an output signal on an output node responsive to said activating;
• capturing, in a storage element, a logic value of the input signal responsive to the clock signal transitioning to the second logic level;
• deactivating the output stage responsive to the clock signal transitioning from the second logic level to the first logic level;
• storing, in the storage element, the logic value of the input signal subsequent to the clock signal transitioning from the second logic level to the first logic level;
• and
• providing the output signal, from the storage element, subsequent to the clock signal transitioning from the second logic level to the first logic level.

An electronic circuit comprising:

• a clock input circuit coupled to receive a clock signal;
• an output circuit configured to drive an output signal on an output node;
• an activation circuit coupled to the clock input circuit and the output circuit, wherein the activation circuit is configured to configured to activate the output circuit responsive to detecting a transition of an input signal on an input node and a transition of the clock signal from a first level to a second level;
• and
• a storage circuit coupled to the activation circuit and the output node and configured to capture and store a logic value of the input signal when the clock signal is at the second level;
• wherein the output circuit is configured to, when active, drive the output signal at the logic value of the input signal;
• wherein the activation circuit is configured to inhibit the output circuit when the clock signal returns to the first logic level;
• and
• wherein the storage circuit is configured to provide the output signal at the logic value on the output node responsive to capturing the logic value and subsequent to inhibiting the output circuit.