US 2010/0164572 A1Published application

Semiconductor device

AssigneeHynix Semiconductor Inc.

InventorKyung-Hoon Kim

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

Claims25

Dependent claims

A semiconductor device comprising:

an internal clock signal generating block configured to generate a delay control signal by detecting a phase difference between a reference clock signal and a feedback clock signal, generate an internal clock signal by delaying the reference clock signal for a time corresponding to the delay control signal, and generate the feedback clock signal by reflecting delay of a clock path in the semiconductor device at the internal clock signal;
a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value calculated based on a delay amount between the reference clock signal and the feedback clock signal in response to locking completion information;
and
an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 12/486,320Filed 17 Jun 2009
Priority: KR 10-2008-013738230 Dec 2008
Published: 1 Jul 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization

Family

US 8,030,981 B2Related patent
US 2010/0164572 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key