Delay locked loop circuit and operational method thereof

An operational method of a delay locked loop circuit, the method comprising:

• generating first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal before a delay-locked;
• generating the first internal clock in response to the clock buffering control signal and the second internal clock in response to the clock buffering control signal and a duty correcting operation terminating signal after the delay-locked;
• generating the duty correcting operation terminating signal in response to a precharge control signal and a clock enable signal after the delay-locked;
• outputting first and second delay locking clocks by comparing phases of the first and second internal clocks with those of first and second feedback clocks and reflecting delay values for the delay-locked corresponding to comparison results to the first and second internal clocks, respectively;
• and
• mixing phases of the first and second delay locking clocks in an inactivation period of the duty correcting operation terminating signal.

A delay locked loop circuit, comprising:

• a first clock buffering block configured to generate a first internal clock corresponding to a first edge of a source clock in response to a clock buffering control signal;
• a second clock buffering block configured to generate a second internal clock corresponding to a second edge of the source clock in response to the clock buffering control signal, which is controlled in response to a duty correcting operation terminating signal and a delay locking signal;
• a first delay locking block configured to compare a phase of the first internal clock with that of a first feedback clock to enable a first locking signal according to a delay locking and output a first delay locking clock by delaying the first internal clock as much as a time corresponding to the comparison result;
• a second delay locking block configured to compare a phase of the second internal clock with that of a second feedback clock to enable a second locking signal according to a delay locking and output a second delay locking clock by delaying the second internal clock as much as a time corresponding to the comparison result;
• a duty correcting block configured to mix a phase of the first delay locking clock and that of the second delay locking clock in an inactivation period of the duty correcting operation terminating signal;
• a first signal generating block configured to generate the duty correcting operation terminating signal in response to a clock enable signal, a precharge control signal and the delay locking signal;
• and
• a second signal generating block configured to generate the delay locking signal in response to the first and second locking signals.