Follower output buffer
OwnerDaniele Vimercati, Riccardo Muzzettoinventors
Life of this patent
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Abstract
Embodiments include but are not limited to apparatuses and systems including an output buffer including an input terminal for receiving an input signal, an output terminal for outputting an output signal, and a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage. Other embodiments may be described and claimed.
Claims20
An apparatus comprising:
- an input terminal for receiving an input signal;
- an output terminal for outputting an output signal;
- and
- a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage.
A system comprising:
- an output buffer stage including a follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage;
- and
- a memory device including an output terminal coupled to an input terminal of the output buffer stage;
- a host logic device bus;
- and
- a bus interface unit coupling the output buffer stage and the host logic device bus.
A method comprising:
- receiving an input signal on an input terminal of a follower circuit;
- outputting an output signal by the follower circuit onto a transmission line;
- and
- adaptively matching an impedance of the output signal with an impedance of the transmission line.
Dependencies are inferred from the claim text.