Sample-and-hold (s/h) circuit

A sample-and-hold (S/H) circuit designed to have a long hold time and low voltage droop during hold time, comprising:

• an input operational amplifier having a first inverting input (V−) designed to receive an analog input voltage (VIN) signal, the input operational amplifier designed to generate a source voltage (VS1) signal;
• a sample-and-hold switch, comprising:
• an inverter designed to receive a clock signal (CLK) and to generate an inverted clock signal (ICLK);
• a first switch coupled to a first node;
• a second switch comprising a gate that receives the clock signal (CLK), a source coupled to the first node, a drain coupled to a second node, and a bulk region, wherein the bulk region is electrically coupled to the source;
• and
• a third switch comprising a gate that receives the inverted clock signal (ICLK), a drain coupled to a third node, a source coupled to the first node;
• an integrator circuit, comprising:
• an output operational amplifier having an inverting input (V−) coupled to the drain of the second switch and a non-inverting input (V+) coupled to the third node, wherein the output operational amplifier is designed to generate an output voltage (VOUT) signal at an output thereof;
• and a hold capacitor (CH) capacitor coupled between the second node and the output of the output operational amplifier;
• and
• a bias voltage (VBIAS) source coupled to the third node such that the drain of the third switch and the non-inverting input (V+) of the output operational amplifier are biased at a bias voltage (VBIAS), wherein the bias voltage (VBIAS) source drives a gate-to-source voltage (VGS) of the second switch to a predetermined optimum negative value when operating in a hold mode.

A sample-and-hold (S/H) circuit, comprising:

• a sample-and-hold switch, comprising:
• a first switch comprising comprising a first gate, a first source and a first drain;
• a second switch comprising a second gate that receives a clock signal (CLK), a second source coupled in series to the first drain and, a second drain;
• and a third switch comprising a third gate that receives an inverted clock signal (ICLK), a third drain, and a third source coupled to the first source;
• an integrator circuit designed to generate an output voltage (VOUT) signal, and comprising:
• an output operational amplifier having an output, an inverting input (V−) coupled to the second drain, and a non-inverting input (V+);
• a storage device having a first terminal coupled to the output of the integrator circuit and a second terminal coupled to the inverting input of the integrator circuit;
• and
• a bias voltage (VBIAS) source coupled to the third drain and the non-inverting input (V+) of the integrator circuit to apply a bias voltage (VBIAS) to the third drain and the non-inverting input (V+) of the integrator circuit, wherein the third switch and the bias voltage (VBIAS) source operate during a hold mode to drive a gate-to-source voltage (VGS) of the second switch to an optimum negative value.