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US 2010/0164543 A1Published application
Low-complexity electronic adder circuits and methods of forming the same
OwnerDaniel R. Shepardinventor
Life of this patent
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Abstract
In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.
Claims20
An electronic device comprising:
- an adder circuit comprising a plurality of transistors of a single type selected from the group consisting of NMOS transistors and PMOS transistors,
- wherein the adder circuit dissipates no more power than an equivalent CMOS circuit.
A memory device comprising:
- a memory array comprising a plurality of generally parallel rows and a plurality of generally parallel columns intersecting the plurality of rows;
- a memory cell proximate an intersection of a row and a column, the memory cell comprising a resistive-change material;
- and
- an adder circuit electrically connected to the memory array, the adder circuit comprising a plurality of transistors;
- wherein all of the transistors of the adder circuit are of a single type selected from the group consisting of PMOS transistors and NMOS transistors.
2 more elements
A method of forming an electronic device, the method comprising:
- providing an adder circuit comprising a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors,
- wherein the adder circuit dissipates no more power than an equivalent CMOS circuit.
A method of forming an electronic device, the method comprising:
- performing plurality of process steps to form an adder circuit, the adder circuit comprising a plurality of transistors,
- wherein number of process steps is less than a number of process steps required to fabricate an equivalent CMOS circuit.
Dependencies are inferred from the claim text.