Semiconductor device and semiconductor testing method

A method for testing a semiconductor device having plural flip-flops, and a combinational circuit which receives the outputs of the plural flip-flops, said method comprising the steps of:

• holding values of test vectors for a quiescent power supply current test in the flip-flops until inputting of the test vectors to all the flip-flops in a scan chain is completed;
• rewriting the values of the test vectors in the flip-flops to values of next test vectors when inputting of the next test vectors to all the flip-flops is completed, and holding the values of the rewritten test vectors in the flip-flops after the values of the test vectors in the flip-flops have been rewritten;
• and
• measuring a quiescent power supply current value at an external power supply terminal for the combinational circuit, and comparing the measured current value with a reference current value, when the values of the test vectors in the flip-flops are rewritten to the values of the next test vectors, and the values of the test vectors that have been held in the flip-flops before being rewritten to the next test vectors are input to the combinational circuit, and thereby the quiescent power supply current of the combinational circuit goes into the quiescent mode.

A method for testing a semiconductor device having plural flip-flops and a combinational circuit which receives the outputs from the plural flip-flops, said method comprising the steps of:

• holding values of test vectors for a quiescent power supply current test in the flip-flops until inputting of the test vectors to all the flip-flops in a scan chain is completed;
• rewriting the values of the test vectors in the flip-flops to values of next test vectors when inputting of the next test vectors to all the flip-flops is completed, and holding the values of the rewritten test vectors in the flip-flops after the values of the test vectors in the flip-flops have been rewritten;
• and
• measuring the power supply current values at two or more points at a timing after a predetermined period has passed from when the test vectors are input to the combinational circuit and a timing after a further predetermined period has passed from that timing to calculate an inclination between the two current values, and comparing this inclination with a reference inclination, until the values of the test vectors in the flip-flops are rewritten to the values of the next test vectors, and the values of the test vectors that have been held in the flip-flops before being rewritten to the next test vectors are input to the combinational circuit and thereby the quiescent power supply current of the combinational circuit goes into the quiescent mode.