Wire Structure of Semiconductor Device and Method for Manufacturing the Same

A method for manufacturing a wire structure of a semiconductor device, the method comprising:

• obtaining a layout of an active region in a semiconductor substrate, the layout extending in a direction diagonally intersecting a layout of a bit line;
• forming an isolation layer that delimits the active region;
• forming over the semiconductor substrate a stack of a first insulation layer, an etch stop layer, and a second insulation layer;
• forming a contact hole penetrating the stack;
• forming over the second insulation layer a first mask layer filling the contact hole;
• forming a first mask pattern exposing a portion of the second insulation layer according to the layout of the bit line, with accompanying of a filler, which fills the contact hole, by patterning the first mask layer;
• selectively etching the exposed portion of the second insulation layer using the first mask pattern and the filler as an etch mask to form a trench exposing a surface of the etch stop layer over a bottom thereof and partially overlapping with the contact hole;
• selectively removing the first mask pattern and the filler;
• forming a spacer over a side wall of the trench and a side wall of the contact hole;
• forming a bit line contact which fills the contact hole and the bit line which partially fills the trench to expose an upper side part of the spacer;
• forming a capping layer over the bit line, the capping layer filling the trench to be connected to the spacer and protecting the upper part of the bit line;
• performing, on the second insulation layer, a Self Aligned Contact (SAC) etch process using the capping layer and the spacer as an etch barrier to form a storage node contact hole that penetrates the stack;
• and,
• forming a storage node contact filling the storage node contact hole.

A wire structure of a semiconductor device, the structure comprising:

• a semiconductor substrate comprising an isolation region that delimits an active region;
• a stack disposed over the semiconductor substrate, the stack comprising a first insulation layer, an etch stop layer, and a second insulation layer;
• a bit line having a layout extending in a direction diagonally intersecting the active region and partially filling a trench formed in such a way that a portion of the second insulation layer is etched to expose a surface of the etch stop layer;
• a bit line contact filling a contact hole that penetrates the stack and overlaps the bit line;
• a capping layer filling up the trench to protect an upper part of the bit line and having an upper surface with a height equal to that of the second insulation layer;
• and
• a spacer disposed between a side wall of the trench and the bit line and a side wall of the contact hole and the bit line contact, the spacer having an upper part connected to the capping layer.