Semiconductor process, and silicon substrate and chip package structure applying the same

A chip package structure, comprising:

• a silicon base, comprising a stair structure, wherein the stair structure has a first notch with a first depth and a second notch with a second depth, the first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch;
• an insulating layer, disposed on the silicon base and covering the first notch and the second notch;
• a metal seed layer, covering the insulating layer located above the first notch;
• a circuit layer, covering the metal seed layer located above the first notch;
• a chip, disposed in the second notch, wherein an upper surface of the chip is lower than the circuit layer, and the chip is electrically connected to the circuit layer through a plurality of conductive wires;
• a molding compound, encapsulating the insulating layer, the metal seed layer, the circuit layer, the chip, and the plurality of conductive wires, wherein the molding compound and the circuit layer are substantially aligned to each other;
• and
• at least a metal pad, disposed on the circuit layer and exposed by the molding compound.