Non-Conductive Planarization of Substrate Surface for Mold Cap

A packaging substrate having a substantially planar surface, the substrate comprising:

• a laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart a an interval greater than a predetermined minimum air-vein forming distance;
• a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance;
• and
• a solder mask applied over the substrate to cover the top metal layer and non-conducting material.

An integrated circuit device device comprising:

• an IC die mounted in a die attach area in a laminate substrate, the laminate substrate having a surface divided into a area inside an encapsulation boundary region and an area outside the encapsulation boundary region, the die attach area within the area inside the encapsulation boundary, the IC die encapsulated with a molding compound within the encapsulation boundary region;
• the laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart at an interval greater than a predetermined minimum air-vein forming distance, each conductive trace having an inner connection located inside the encapsulation boundary and an outer connection located outside the encapsulation boundary region, the inner connection of each conductive trace connecting the IC die at predefined pads;
• and
• a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces across the encapsulation boundary region, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance.