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US 2010/0164080 A1Published application
Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorYoshiaki GOTO
Life of this patent
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Abstract
A semiconductor device includes a circuit base including an inner lead portion and an outer lead portion. The inner lead portion has a plurality of inner leads. At least part of the inner leads is routed inside a chip mounting area. On both upper and lower surfaces of the circuit base, a first and a second semiconductor chip are mounted. At least part of electrode pads of the first semiconductor chip are electrically connected to electrode pads of the second semiconductor chip via the inner leads.
Claims20
A semiconductor device, comprising:
- a circuit base including a chip mounting area, an outer lead portion having a plurality of outer leads, and an inner lead portion having a plurality of inner leads, at least part of the inner leads being routed inside the chip mounting area;
- a first semiconductor chip group, disposed on the chip mounting area in a first surface of the circuit base, including at least one first semiconductor chip having first electrode pads;
- a second semiconductor chip group, disposed on the chip mounting area in a second surface of the circuit base, including at least one second semiconductor chip having second electrode pads;
- first metal wires electrically connecting the first electrode pads of the first semiconductor chip and the inner lead portion;
- second metal wires electrically connecting the second electrode pads of the second semiconductor chip and the inner lead portion;
- and
- a resin sealing portion sealing the first and second semiconductor chip groups together with the first and second metal wires,
- wherein at least part of the first electrode pads of the first semiconductor chip are electrically connected to the second electrode pads of the second semiconductor chip via the inner leads.
5 more elements
A semiconductor device, comprising:
- a circuit base including a chip mounting area, a first outer lead portion having first outer leads, a second outer lead portion having second outer leads opposed to the first outer leads via the chip mounting area, and an inner lead portion having first inner leads connected to the first outer leads, second inner leads connected to the second outer leads and third inner leads electrically independent of the first and second outer leads, at least part of the first, second, and third inner leads being routed inside the chip mounting area;
- a first semiconductor chip group, disposed on the chip mounting area in a first surface of the circuit base, including at least one first semiconductor chip having first electrode pads;
- a second semiconductor chip group, disposed on the chip mounting area in a second surface of the circuit base, including at least one second semiconductor chip having second electrode pads;
- first metal wires electrically connecting the first electrode pads of the first semiconductor chip and the inner lead portion;
- second metal wires electrically connecting the second electrode pads of the second semiconductor chip and the inner lead portion;
- and
- a resin sealing portion sealing the first and second semiconductor chip groups together with the first and second metal wires,
- wherein at least part of the first electrode pads of the first semiconductor chip are electrically connected to the second electrode pads of the second semiconductor chip via the third inner leads.
5 more elements
Dependencies are inferred from the claim text.