Electrical passivation of silicon-containing surfaces using organic layers

A process for forming an electrical device comprising:

• forming a patterned insulating layer over at least of the electrical device, wherein:
• the patterned insulating layer defines an opening;
• a silicon-containing region has an exposed portion at the opening;
• and
• the silicon-containing region is at least part of an electrical component within the electrical device;
• forming an organic layer chemically bonded to the surface of the silicon-containing region;
• removing the organic layer;
• and
• forming a metal-containing layer after removing the organic layer, wherein at least a portion of the metal-containing layer contacts the exposed portion of the silicon-containing region, and wherein the metal-containing layer is part of an electrical connection to the silicon-containing region.

A process for forming an electrical device comprising:

• forming a patterned insulating layer over at least of the electrical device, wherein:
• the patterned insulating layer defines an opening;
• a silicon-containing region has an exposed portion at the opening;
• and
• the silicon-containing region is at least part of an electrical component within the electrical device;
• forming an organic layer chemically bonded to the surface of the crystalline material;
• removing the organic layer;
• and
• forming a dopant-source layer that contacts the exposed portion of the silicon-containing region.