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US 2010/0164014 A1Published application
Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities
AssigneeAdvanced Micro Devices, Inc.
InventorsStephan Kronholz, Andreas Ott
Life of this patent
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Abstract
A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.
Claims25
A method, comprising:
- forming a layer of a silicon-containing semiconductor alloy on a first silicon-containing crystalline semiconductor region and a second silicon-containing crystalline semiconductor region;
- removing said layer of silicon-containing semiconductor alloy selectively from said second silicon-containing crystalline semiconductor region;
- forming a first gate electrode structure of a first transistor on said layer of a silicon-containing semiconductor alloy, said first gate electrode structure comprising a high-k dielectric gate insulation layer and a metal-containing gate electrode material formed on said high-k dielectric gate insulation layer;
- and
- forming a second gate electrode structure of a second transistor above said second silicon-containing crystalline semiconductor region, said second gate electrode structure comprising a high-k dielectric gate insulation layer and a metal-containing gate electrode material formed on said high-k dielectric gate insulation layer of said second gate electrode structure.
2 more elements
A method, comprising:
- forming a threshold adjusting semiconductor material on first and second silicon-containing semiconductor regions;
- introducing a dopant species in said second silicon-containing semiconductor region by using an implantation mask covering said first silicon-containing semiconductor region;
- removing said threshold adjusting semiconductor material selectively from said second silicon-containing semiconductor region on the basis of said implantation mask;
- and
- forming a first gate electrode structure of a first transistor on said threshold adjusting semiconductor material and a second gate electrode structure of a second transistor on said second silicon-containing semiconductor region, said first and second gate electrode structures comprising a high-k dielectric material and a metal-containing electrode material formed on said high-k dielectric material.
2 more elements
A semiconductor device, comprising:
- a first device region comprising a plurality of densely packed first P-channel transistors defining a pitch of approximately 100 nm or less, each of said first P-channel transistors being formed in and above a first silicon-containing semiconductor region and comprising a first layer of a threshold adjusting semiconductor alloy in a channel region of each of said first P-channel transistors;
- and
- a second device region comprising a plurality of second P-channel transistors defining a pitch of more than 100 nm, each of said second P-channel transistors being formed in and above a second silicon-containing semiconductor region and comprising a second layer of said threshold adjusting semiconductor alloy in a channel region of each of said second P-channel transistors, wherein a degree of uniformity of at least one of a material composition and a layer thickness of said first and second layers of said threshold adjusting semiconductor alloy is approximately plus/minus 2 percent.
Dependencies are inferred from the claim text.