Semiconductor device for improving channel mobility

An SRAM cell array, comprising:

• a plurality of SRAM cells including a transfer transistor, a driver transistor, and a load transistor;
• a first source contact formed on a source region of the driver transistor;
• a first drain contact formed on a drain region of the driver transistor;
• a tensile film configured to generate a tensile stress in a channel region of the driver transistor;
• a second source contact formed on a source region of the load transistor;
• and
• a second drain contact formed on a drain region of the load transistor,
• wherein a first distance between the first source contact and a gate electrode of the driver transistor is greater than a second distance between the first drain contact and the gate electrode of the driver transistor, and
• wherein the tensile film is formed on the load transistor and a third distance between the second drain contact and a gate electrode of the load transistor is less than a fourth distance between the second drain contact and the gate electrode of the load transistor.

An SRAM cell array, comprising:

• a plurality of SRAM cells including a transfer transistor, a driver transistor, and a load transistor;
• a first source contact formed on a source region of the driver transistor;
• a first drain contact formed on a drain region of the driver transistor;
• a tensile film configured to generate a compressive stress in a channel region of the driver transistor;
• a second source contact formed on a source region of the load transistor;
• and
• a second drain contact formed on a drain region of the load transistor,
• wherein a first distance between the first source contact and a gate electrode of the driver transistor is less than a second distance between the first drain contact and the gate electrode of the driver transistor, and
• wherein the compressive film is formed on the load transistor and a third distance between the second drain contact and a gate electrode of the load transistor is greater than a fourth distance between the second drain contact and the gate electrode of the load transistor.