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US 2010/0164008 A1Published application
Method for integration of replacement gate in cmos flow
AssigneeTexas Instruments Incorporated
InventorsFreidoon Mehrad, James J. Chambers, Shaofeng Yu
Life of this patent
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Abstract
Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.
Claims20
A method of fabricating an integrated circuit, including PMOS and NMOS replacement gate structures in a semiconductor device, the method comprising:
- forming disposable gate structures over a gate dielectric in PMOS and NMOS regions of a semiconductor body;
- forming a BTBAS layer over the disposable gate structures;
- planarizing the BTBAS layer to expose a top portion of the disposable gate structures;
- removing the disposable gate structures in the NMOS region to expose the gate dielectric in the NMOS region;
- forming an NMOS metal capping layer over the gate dielectric in the NMOS region;
- forming an NMOS first metal layer over the NMOS metal capping layer in the NMOS region;
- forming a conductive first gap fill layer over the NMOS first metal layer in the NMOS region;
- removing the disposable gate structure in the PMOS region to expose the gate dielectric in the PMOS region;
- forming a PMOS second metal layer over the gate dielectric in the PMOS region;
- and
- forming a conductive second gap fill layer over the PMOS second metal layer in PMOS region.
8 more elements
A method of fabricating an integrated circuit, including PMOS and NMOS replacement gate structures in a semiconductor device, the method comprising:
- forming disposable gate structures over a gate dielectric in both PMOS and NMOS regions;
- forming a BTBAS layer over the disposable gate structures in the PMOS and NMOS regions;
- planarizing the BTBAS layer, thereby exposing a top portion of the disposable gate structures in the PMOS and NMOS regions;
- masking the PMOS region and then removing the disposable gate structure to form a cavity having a gate dielectric exposed therein at a bottom thereof in the NMOS region;
- forming an NMOS metal capping layer over the exposed gate dielectric in the bottom of the cavity in the NMOS region;
- forming an NMOS first metal layer over the NMOS metal capping layer in the cavity in the NMOS region;
- forming a conductive first gap fill layer over the NMOS first metal layer thereby filling the cavity in the NMOS region;
- masking the NMOS region and then removing the disposable gate structure to form a cavity having a gate dielectric exposed therein at a bottom portion thereof in the PMOS region;
- forming a PMOS second metal layer over the gate dielectric in the PMOS region;
- and
- forming a conductive second gap fill layer over PMOS second metal layer in PMOS region.
8 more elements
A method of fabricating an integrated circuit, including PMOS and NMOS replacement gate structures in a semiconductor device, the method comprising:
- forming polysilicon disposable gate structures having an insulative hardmask thereover over a gate dielectric in PMOS and NMOS regions of a semiconductor body, wherein the disposable gate structures define source/drain areas in the semiconductor body on opposing sides thereof;
- forming source/drain regions in the source/drain areas in the PMOS and NMOS regions, respectively;
- siliciding the source/drain regions in the PMOS and NMOS regions while the insulative hardmask prevents silicidation of the polysilicon gate structures in the PMOS and NMOS regions;
- forming a BTBAS layer over the silicided source/drain regions and over the polysilicon disposable gate structures in the PMOS and NMOS regions;
- planarizing the BTBAS layer to expose a top portion of the polysilicon disposable gate structures in the PMOS and NMOS regions;
- masking the PMOS region and performing a dry etch to remove a first portion of the polysilicon disposable gate structure in the NMOS region;
- performing a wet etch to remove a remaining portion of the polysilicon disposable gate structure in the NMOS region, thereby generating a cavity exposing the gate dielectric at a bottom portion thereof in the NMOS region, wherein the BTBAS layer protects underlying silicided source/drain regions in the NMOS region during the wet etch;
- forming an NMOS metal capping layer over the exposed gate dielectric in the bottom of the cavity in the NMOS region;
- forming an NMOS first metal layer over the NMOS metal capping layer in the cavity in the NMOS region;
- forming a conductive first gap fill layer over the NMOS first metal layer thereby filling the cavity in the NMOS region;
- masking the NMOS region and performing a dry etch to remove a first portion of the polysilicon disposable gate structure in the PMOS region;
- performing a wet etch to remove a remaining portion of the polysilicon disposable gate structure in the PMOS region, thereby generating a cavity exposing the gate dielectric at a bottom portion in the PMOS region, wherein the BTBAS layer protects underlying silicided source/drain regions in the PMOS region during the wet etch;
- forming a PMOS second metal layer over the gate dielectric in the PMOS region;
- and
- forming a conductive second gap fill layer over PMOS second metal layer in PMOS region.
12 more elements
Dependencies are inferred from the claim text.