US 2010/0164004 A1 · METHODS FOR REDUCING GATE DIELECTRIC THINNING ON TRENCH ISOLATION EDGES AND INTEGRATED CIRCUITS THEREFROM

Abstract

A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed.

Claims18

Dependent claims

A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors, comprising:

providing a substrate having a silicon comprising surface;
forming a plurality of dielectric filled trench isolation regions in said substrate, wherein said silicon comprising surface forms trench isolation active area edges along its periphery with said trench isolation regions;
depositing a first silicon comprising layer, said first silicon comprising layer extending from a surface of said trench isolation regions over said trench isolation active area edges to said silicon comprising surface;
oxidizing said first silicon comprising layer to completely convert said first silicon layer to a silicon oxide layer, wherein said silicon oxide layer provides at least a portion of a gate dielectric for at least one of said plurality of MOS transistors,
forming a patterned gate electrode layer over said gate dielectric, wherein said patterned gate electrode layer extends over at least one of said trench isolation active area edges to said silicon comprising surface, and
completing fabrication of said IC.

3 more elements

An integrated circuit (IC), comprising:

a substrate having a silicon comprising surface;
a plurality of MOS transistors formed in or on said substrate, said MOS transistors comprising a first plurality of MOS transistors in first regions of said substrate, said gate dielectric for said first plurality of MOS transistors having a first gate dielectric thickness, and at least a second plurality of MOS transistors in second regions of said substrate, said gate dielectric for said second plurality of MOS transistors having a second gate dielectric thickness, wherein said first gate dielectric thickness is at least 10%> said second gate dielectric thickness,
wherein said first plurality of MOS transistors comprise:
a plurality of dielectric filled trench isolation regions in said substrate, wherein said silicon comprising surface forms trench isolation active area edges along its periphery with said trench isolation regions;
a patterned gate stack comprising a patterned gate electrode on a gate dielectric layer comprising primarily a thermally grown silicon oxide comprising layer formed on said silicon comprising surface, wherein said patterned gate electrode layer extends over said trench isolation active area edges, and
source and drain regions formed in or on said silicon comprising surface on opposite sides of said gate stack,
wherein said first gate dielectric thickness of said thermally grown silicon oxide comprising gate dielectric layer over said trench isolation active area edges in said first regions is at least 95% of a thickness of gate dielectric layer over said silicon comprising surface 0.3 μm away from said trench isolation active area edges, said thickness over said silicon comprising surface away from said trench isolation active area edges being from 300 to 5,000 Angstroms, and wherein said gate dielectric layer has a surface roughness corresponding to local area variations of said first gate dielectric thickness being at least 10 Angstroms.

4 more elements

Dependencies are inferred from the claim text.

Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom

Life of this patent

Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom

Life of this patent

Abstract

Claims18