US 2010/0163994 A1Published application

Soi device with a buried insulating material having increased etch resistivity

AssigneeAdvanced Micro Devices, Inc.

InventorsAndreas Kurz, Roman Boschke, Christoph Schwan, John Morgan

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Abstract

In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

Claims25

Dependent claims

A method of forming a semiconductor device, the method comprising:

providing a buried insulating material formed above a crystalline substrate material at least in a first device region, said buried insulating material having an increased etch resistivity as compared to silicon dioxide formed by an oxidation process with respect to a wet chemical cleaning recipe to be performed prior to forming a metal silicide in said crystalline substrate material and a semiconductor layer formed above said crystalline substrate material in at least a second device region;
forming an opening through said buried insulating material in said first device region so as to expose a portion of said crystalline substrate material;
forming drain and source regions of a transistor in said semiconductor layer in said second device region and a doped region in said crystalline substrate material exposed by said opening in a common implantation process;
performing one or more cleaning processes on the basis of said wet chemical cleaning recipe;
and
forming a metal silicide in said transistor and said doped region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/639,515Filed 16 Dec 2009
Priority: DE 10 2008 063 403.431 Dec 2008
Published: 1 Jul 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…
H10D 84/0109
Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00,…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 86/01
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…

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US 8,617,940 B2Related patent
US 2010/0163994 A1This patent

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