Semiconductor Device Having Saddle Fin Transistor and Method for Fabricating the Same

A semiconductor device having a saddle fin transistor, comprising:

• a semiconductor substrate having a cell region and a peripheral circuit region;
• a saddle fin gate disposed in the cell region under a surface of the semiconductor substrate;
• a stack type gate disposed over the peripheral circuit region of the semiconductor substrate;
• an insulation layer covering the saddle fin gate, the insulation layer exposing a contact region in the cell region;
• and
• a contact plug in the contact region exposed by the insulation layer in the cell region.

A method for fabricating a semiconductor device having a saddle fin transistor, comprising:

• forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate;
• forming a trench in the isolation region of the semiconductor substrate;
• forming an isolation layer within the trench;
• etching an active region of the semiconductor substrate by a selected depth to form a recessed active region;
• etching the isolation layer by a selected depth to form a recessed isolation region;
• depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor;
• forming an insulation layer over an upper portion of the gate;
• removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug;
• and
• depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

A method for fabricating a semiconductor device having a saddle fin transistor, comprising:

• forming a pad nitride layer that exposes an isolation region over a cell region and a peripheral circuit region of a semiconductor substrate;
• forming a trench isolation layer in the isolation region of the semiconductor substrate;
• recessing a portion of an active region to be formed with a channel by a selected depth;
• recessing a portion of the trench isolation layer to form a saddle fin shape;
• forming a saddle fin gate buried under a surface of the semiconductor substrate in the recessed active region;
• forming an insulation layer over an upper portion of the saddle fin gate to isolate the saddle fin gate;
• removing the pad nitride layer to expose a portion of the semiconductor substrate in the cell region to be formed with a contact plug and the peripheral circuit region of the semiconductor substrate;
• forming a gate insulation layer over the peripheral circuit region of the semiconductor substrate;
• forming a conductive layer over the cell region;
• forming a conductive layer over the peripheral circuit region of the semiconductor substrate;
• and
• etching the conductive layers to form a contact plug in the cell region and a stack type gate in the peripheral circuit region.