Cmos image sensor having double gate insulator therein and method for manufacturing the same

A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:

• a semiconductor substrate having a first area and a second area, wherein the first area is substantially surrounded by the second area and is isolated from the second area by a field oxide region;
• a pixel array formed in the first area of the semiconductor substrate, wherein the pixel array includes a plurality of MOSFET transistors each having a gate with a gate insulating layer;
• and
• a logic circuit formed in the second area of the semiconductor substrate, wherein the logic circuit includes a plurality of MOSFET transistors each having a gate with a gate insulating layer;
• wherein the gate insulating layer of each MOSFET transistor in the pixel array is thicker than the gate insulating layer of each MOSFET transistor in the logic circuit.

A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:

• a semiconductor substrate including a first area and a second area, wherein the first and second areas are isolated from one another by an isolation region;
• pixel sensors formed by MOSFET transistors in the first area and arranged in a pixel array, wherein each of the MOSFET transistors in the first area has a gate with a gate insulating layer of a first thickness;
• and
• a logic circuit formed by MOSFET transistors in the second area, wherein the MOSFET transistors in the second area have gates with gate insulating layers of a second thickness;
• wherein the first thickness is greater than the second thickness.

A method of making a complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising:

• doping regions in a substrate to form MOSFET transistors in first and second areas of the substrate, wherein the MOSFET transistors in the first area are used to form pixel sensors of a pixel array, and wherein the MOSFET transistors in the second area are used to form a logic circuit;
• forming a field oxide in a region around the first area to isolate the MOSFET transistors in the first area from the MOSFET transistors in the second area;
• depositing a first insulating layer concurrently over both the first and second areas of the substrate;
• removing the first insulating layer from the second area while leaving the first insulating layer over the first area intact;
• depositing a second insulating layer concurrently over both the first and second areas of the substrate;
• removing the second insulating layer from selected regions of the second area to form gates of the MOSFET transistors in the logic circuit;
• and
• removing both the first and second gate insulating layers from selected areas of the first area to form gates of the MOSFET transistors of the pixel sensors, wherein the gate of each MOSFET transistor in the first area has a thickness corresponding to a combined thickness of the first and second insulating layers, and wherein the gate of each MOSFET transistor in the second area has a thickness that is less than a combined thickness of the first and second insulating layers.

A method of making a complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising:

• growing an epitaxial layer on a surface of a substrate;
• doping a first area of the substrate for forming MOSFET transistors of a plurality of pixel sensors in a pixel array;
• doping a second area of the substrate for forming MOSFET transistors of a logic circuit;
• depositing a field oxide in the epitaxial layer in a region around the first area to isolate the pixel array from the logic circuit;
• depositing a first insulator layer over the first and second areas during a first deposition process;
• removing the first insulator layer from the second area of the substrate;
• depositing a second insulator layer over the first and second areas during a second deposition process;
• patterning the first and second insulator layers in the first area to form gates of the MOSFET transistors in the pixel array;
• and
• patterning the second insulator layer in the second area to form gates of the MOSFET transistors of the logic circuit.