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US 2010/0163835 A1Published application
Controlling the circuitry and memory array relative height in a phase change memory feol process flow
AssigneeMicron Technology, Inc.
InventorsMarcello Mariani, Lorenzo Frantin, Anna Rita Odorizzi, Michele Magistretti
Life of this patent
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Abstract
A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of the CMOS logic portion with the PCM portion is described.
Claims18
A Phase Change Memory (PCM) device, comprising:
- an array portion for memory storage that includes junction devices;
- and
- a circuitry portion for CMOS combinational logic devices that is recessed during fabrication to provide substantial planarity with the array portion.
A device, comprising:
- a selector junction device coupled to a phase change material in a Phase Change Memory (PCM);
- and
- a CMOS section embedded with the PCM having been recessed by a height that substantially matches a height of a gate oxide and a polysilicon gate to provide planarity of the CMOS section with the PCM.
A method of embedding a Phase-Change Memory (PCM) portion with a CMOS logic portion, comprising:
- recessing a core processor section in the CMOS logic portion;
- protecting the PCM portion with a nitride layer from oxidation;
- and
- removing a recession oxidation below a surface of the PCM portion by a combined thickness of a gate oxide and a polysilicon gate.
1 more element
A wireless communications device, comprising:
- a transceiver to receive a modulated signal;
- a Phase-Change Memory (PCM) portion having memory cells with a selector Bipolar Junction Transistor (BJT) device coupled to a phase change material;
- and
- a CMOS logic portion having multiple processor cores embedded with the PCM portion that is coupled to the transceiver to receive the modulated signal, wherein the CMOS logic portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to provide planarity of a lowered surface of the CMOS logic portion with a surface of the PCM portion.
1 more element
Dependencies are inferred from the claim text.