Ovonic threshold switch film composition for tslags material
AssigneeSTMicroelectronics S.r.l.
InventorsStanford Ovshinsky, Tyler Lowrey, James D. Reed
Life of this patent
Estimating the term…
Abstract
A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.
Claims24
A chalcogenide alloy, comprising:
- AsmXqGerSitNz
- wherein:
- m is an atomic percentage of the alloy in the range of 9 to 39;
- q is an atomic percentage of the alloy in the range of 17 and 60;
- r is an atomic percentage of the alloy in the range of 10 and 40;
- t is an atomic percentage of the alloy in the range of 5 and 18;
- z is an atomic percentage of the alloy in the range of 0 and 10;
- X is SaSedTeg wherein,
- a/d is in the range of 0.25 and 4;
- and
- a/g is in the range of 0.11 and 1.
An ovonic threshold switch, comprising:
- a chalcogenide alloy having the following formula:
- AsmXqGerSitNz
- wherein:
- m is an atomic percentage of the alloy in the range of 9 to 39;
- q is an atomic percentage of the alloy in the range of 17 and 60;
- r is an atomic percentage of the alloy in the range of 10 and 40;
- t is an atomic percentage of the alloy in the range of 5 and 18;
- z is an atomic percentage of the alloy in the range of 0 and 10;
- X is SaSedTeg wherein,
- a/d is in the range of 0.25 and 4;
- and
- a/g is in the range of 0.11 and 1.
A phase change memory cell, comprising:
- a phase change memory layer;
- and
- an ovonic threshold switch layer formed of a chalcogenide alloy, comprising:
- AsmXqGerSitNz
- wherein:
- m is an atomic percentage of the alloy in the range of 9 to 39;
- q is an atomic percentage of the alloy in the range of 17 and 60;
- r is an atomic percentage of the alloy in the range of 10 and 40;
- t is an atomic percentage of the alloy in the range of 5 and 18;
- z is an atomic percentage of the alloy in the range of 0 and 10;
- X is SaSedTeg wherein,
- a/d is in the range of 0.25 and 4;
- and
- a/g is in the range of 0.11 and 1.
A memory, comprising:
- a wordline;
- a bitline;
- a phase change memory layer;
- a first electrode that separates the phase change memory layer from the wordline;
- an ovonic threshold switch layer formed of a chalcogenide alloy, comprising:
- AsmXqGerSitNz
- wherein:
- m is an atomic percentage of the alloy in the range of 9 to 39;
- q is an atomic percentage of the alloy in the range of 17 and 60;
- r is an atomic percentage of the alloy in the range of 10 and 40;
- t is an atomic percentage of the alloy in the range of 5 and 18;
- z is an atomic percentage of the alloy in the range of 0 and 10;
- X is SaSedTeg wherein,
- a/d is in the range of 0.25 and 4;
- and
- a/g is in the range of 0.11 and 1;
- a second electrode that separates the ovonic threshold switch from the phase change memory layer;
- and
- a third electrode that separates the ovonic threshold switch from the bitline.
Dependencies are inferred from the claim text.