High Speed Reduced Area Cell Library With Cells Having Integer Multiple Track Heights

A mixed-height cell library for designing integrated circuits, comprising:

• a first plurality of cells having a first track height;
• a second plurality of cells having a second track height and configured to be coupled to the first plurality of cells at respective power and ground rail lines;
• wherein the second track height is an integer multiple of the first track height;
• and
• wherein a cell in the second plurality of cells of the second track height is formed by extending active areas of a corresponding cell in the first plurality of cells of the first track height while maintaining the same distance between power and ground rails.

A method to create a mixed-height cell library comprising:

• forming a first plurality of cells of a first track height;
• and
• forming a second plurality of cells of a second track height that is an integer multiple of first track height by mirroring a corresponding cell of the plurality of cells of the first track height over a horizontal axis that passes through a power rail line of the cell;
• wherein a first cell from the first plurality of cells and a second cell from a second plurality of cells are formed so as to enable coupling at their respective power and ground rail lines.

A method to create a mixed-height cell library comprising:

• forming a first plurality of cells of the first track height;
• and
• forming a second plurality of cells of a second track height that is an integer multiple of first track height by extending active areas of a corresponding cell the first plurality of cells of the first track height while maintaining the same distance between power and ground rails as in the cell of the first track height;
• wherein a first cell from the first plurality of cells and a second cell from a second plurality of cells are formed so as to enable coupling at their respective power and ground rail lines.