Semi-absolute branch instructions for efficient computers
AssigneeSun Microsystems, Inc.
InventorsPaul Caprioli, Peter B. Kessler, Christopher A. Vick
Life of this patent
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Abstract
Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.
Claims14
An apparatus comprising:
- a memory capable of storing a semi-absolute branch instruction at a memory address, said semi-absolute branch instruction comprising a semi-absolute branch instruction opcode, a semi-absolute branch instruction partial address, and a semi-absolute branch instruction adjust bit;
- and
- a computation processor comprising:
- a program-counter comprising a lower bit-range and a higher bit-range, said lower bit-range containing a lower program-counter value;
- an instruction fetch logic responsive to the program-counter and configured to access said semi-absolute branch instruction from the memory at said memory address covered by said program-counter;
- a first instruction decoder logic configured to recognize said semi-absolute branch instruction opcode;
- and
- a first semi-absolute branch instruction logic, responsive to the first instruction decoder logic configured to replace said lower program-counter value of said lower bit-range of said program-counter with said semi-absolute branch instruction partial address.
A method for a computation processor to determine a branch target address, said method comprising:
- selecting a semi-absolute branch instruction responsive to a program-counter within said computation processor, wherein said semi-absolute branch instruction comprises a semi-absolute branch instruction opcode, a semi-absolute branch instruction partial address, and a semi-absolute branch instruction adjust bit, and wherein said program-counter comprises a lower bit-range and a higher bit-range, said lower bit-range containing a lower program-counter value;
- and
- replacing said lower program-counter value in said lower bit-range with said semi-absolute branch instruction partial address.
A computer-implemented method for constructing a semi-absolute branch instruction for subsequent execution by a computation processor, said computation processor comprising a program-counter, said semi-absolute branch instruction including a semi-absolute branch instruction operand, said method comprising:
- determining a program-counter value from where in a memory said semi-absolute branch instruction will be executed by said computation processor;
- determining a branch target address that will replace said program-counter value in said program-counter if execution of said semi-absolute branch instruction were to cause said computation processor to branch, said branch target address comprising a lower bit-range containing a lower program-counter value;
- and
- specifying that said semi-absolute branch instruction operand is to contain said lower program-counter value when said semi-absolute branch instruction is stored at a memory address in said memory that corresponds to said program-counter value for execution by said computation processor when said program-counter contains said program-counter value.
Dependencies are inferred from the claim text.