System and Methods for Parametric Test Time Reduction

A parametric test time reduction system for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range wherein a result of the test is considered a passing result if said result falls within said known pass value range, the method comprising:

• a parametric test range estimator operative, for at least one parametric test, to compute an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing said test on said set will statistically fall at said given confidence level, said validation set defining a complementary set including all semiconductors included in said population and not included in said validation set;
• and
• a parameter test disabler at least partly disabling said at least one parametric test based at least partly on a comparison of said estimated maximum test range and said known pass value range.